Field
The present invention relates to electronic circuits and, more particularly, to programmable clock dividers.
Background
A programmable clock divider receives an input clock signal at an input frequency and produces an output clock signal at an output frequency with the ratio of the input frequency to the output frequency set by a programmable divide ratio. Programmable clock dividers are used in many electronic devices. For example, a programmable clock divider can be used to implement multiple frequencies of operation for a Display Serial Interface (DSI) link between a processor and a display device. DSI is an interface standard established by the Mobile Industry Processor Interface (MIPI) Alliance. The DSI link may operate at many different frequencies, for example, depending on characteristics of the display, with a clock signal toggling at the different frequencies produced by a programmable clock divider.
FIG. 1 is a block diagram of an electronic system that includes a programmable clock divider. The system includes a DSI interface 20. The DSI interface 20 is coupled to DSI signals for communication with a display device 10. The DSI interface 20 may receive data signals and format the signals for communication according to DSI specifications. The DSI interface 20 receives a clock signal (CLKdiv) for use in performing its functions.
A programmable clock divider 45 receives an input clock signal (CLKin) and produces an output clock signal (CLKdiv). The programmable clock divider 45 receives a divide ratio signal (N) that indicates the ratio of the frequency of the input clock signal to the frequency of the output clock signal.
The system of FIG. 1 also includes an SoC block 90. The SoC block 90 provides other functions of the electronic system. The SoC block 90 may supply data to the DSI interface 20. The SoC block 90 may also supply the divide ratio signal and the input clock signal to the programmable clock divider 45.
The clock signal used by the DSI interface 20 may toggle at a wide range of frequencies, for example, 2.5 GHz to 80 MHz. A programmable clock divider that can operate at such high frequencies may be difficult to implement. Additionally, the system may be improved when the delay of the programmable clock divider 45 from the input clock signal to the output clock signal is constant. For example, the SoC block 90 may time some operations using the input clock signal supplied to the programmable clock divider 45. The delay of the programmable clock divider 45 effects the timing of data signals between the SoC block 90 and the DSI interface 20. Thus, a constant delay of programmable clock divider 45 may allow the system to operate at high frequencies. Additionally, functions of circuits in the DSI interface 20 may be improved when the duty cycle of the clock signal used is near 50%. Providing a 50% duty cycle output clock signal is more difficult when the divide ratio is an odd number. Thus, providing a programmable clock divider that produces an output clock signal with a 50% duty cycle, has a constant delay, and operates at high frequencies is valuable.
Many other systems use programmable clock dividers and may have similar requirements.